1. Field of the Invention
The present invention relates in general to computer-aided design (CAD) tool for and in particular to a CAD tool method for calculating peak crosstalk noise in nets of an integrated circuit design.
2. Description of Related Art
A typical integrated circuit (IC) includes circuit components (“cells”) formed within a semiconductor substrate and conductors (“wires”) residing between insulating layers above the substrate providing signal paths (“nets”) between the circuit components. FIG. 1 is a simplified plan view of two simple nets 10 and 12. Net 10 links the output of a driver cell 14 to an input of a receiver cell 16 while net 12 links the output of a driver cell 18 to the output of a receiver cell 20. Based on a netlist description of the circuit referencing the cells that are to be included in a circuit and indicating how their terminals are to be interconnected, and based on a cell library description of the layout of each cell, a computer-aided placement and routing tool can automatically determine where to place each cell 14-20 within the semiconductor substrate and how to route signal paths forming nets 10 and 12 between the cells.
Some amount of coupling capacitance exists between each pair of nets in an IC, so that when a signal edge travels along any one net, the coupling capacitance causes transient charging currents to flow in every other net. The transient charging currents produce transient variations in voltages (“crosstalk noise”) of the signals conveyed by the other nets. The peak magnitude of the crosstalk noise in each “victim” net capacitively coupled to an “aggressor” net conveying the signal edge is a function of such factors as the distance between sections of victim and aggressor nets that are near one another, the lengths of those sections of the victim and aggressor nets, the dielectric constant of the material separating them and relatively timing of the signals they convey. When the crosstalk noise is sufficiently large, it can temporarily drive a signal to a false logic state. Thus it is necessary for the designer to be able to identify nets that are subject to excessive levels of crosstalk noise so that the designer can reroute such nets to reduce crosstalk noise.
The development of deep-submicron technology has allowed IC designers to pack more functionality into ICs by shrinking cell sizes, wire widths and wire spacings. However in moving to deep-submicron technology problems associated with crosstalk noise arise more frequently because the reduced spacing between wires forming nets increases the crosstalk coupling capacitance between them. It is possible to accurately predict peak crosstalk noise but methods for doing so require substantially more computer processing time than less accurate methods for estimating peak crosstalk noise. Fast but relatively inaccurate methods for estimating peak crosstalk are known, but when a designer is able to only roughly estimate peak crosstalk noise, the designer must allow for a relatively large margin of error when deciding whether to reroute a net and will therefore reroute nets more frequently than necessary. This slows the IC development process and reduces the efficiency of the IC layout. Thus with respect to estimating peak crosstalk noise, the designer is faced with a tradeoff between processing time spent accurately estimating peak crosstalk nose and processing time spent rerouting nets.
Crosstalk noise estimates are typically based on the path resistances and capacitances seen by signals passing through the nets. Computer-aided “RC extraction” tools analyze IC layouts to estimate the series resistance and shunt capacitance of various sections of each net. For example FIG. 2 is a schematic diagram modeling networks 10 and 12 of FIG. 1 and their coupling capacitance based on the kind of data provided by an RC extraction too. Resistors 22 and 28 model the series resistances of various sections of nets 10 and 12 and capacitors 24 and 30 model the shunt capacitances of each net section. Capacitors 26 model the coupling capacitance between various sections of nearby nets.
To determine the crosstalk noise in the output signal V0 of a victim net 10 resulting the signals conveyed in aggressor net 12, the designer can program a simulator to simulate the behavior of the circuit model depicted by FIG. 2 wherein signals VV and VA represent the output signals of drivers 14 and 20 of FIG. 1. The nature and relative timing of the VV and VA signal edges are predetermined, based on conventional static timing analysis of the circuit upstream of nets 10 and 12. After the simulator generates waveform data representing behavior of the output voltage VO of victim net 10, that waveform data can be analyzed to determine the amount of crosstalk noise in the VO signal.
The simulation method can predict peak crosstalk noise with relatively high accuracy, but the method can be very time-consuming when used to estimate peak crosstalk noise in every net in a large IC, since an IC can have many thousands of nets. Although the example victim/aggressor model of FIG. 2 is relatively simple in that each network 10 and 12 has only three separately modeled sections, a model of a victim may have many more than three sections and may include branches for delivering a signal from one driver to more than one receiver. Also while FIG. 2 takes into account coupling capacitance between only two networks, several aggressor networks can make significant contributions to crosstalk noise in any one victim network. Therefore a circuit model of a victim net and all aggressor nets substantially contributing to its crosstalk noise will often be much more complicated than the model depicted in FIG. 2, and a circuit simulator will have to spend a substantial amount of processing time carrying out the simulation for each net of an IC.
U.S. Pat. No. 5,568,395 issued Oct. 22, 1996 to Huang, reduces the time needed to estimate crosstalk noise in part by simplifying the model of victim net and its nearby aggressor nets. FIG. 3 represents a model of victim net 10 and aggressor net 12 of FIG. 1 as suggested by Huang. Capacitance CC represents the sum of coupling capacitances 26 (FIG. 2) between the two networks, Cv represents the sum of shunt capacitances 24 of victim net 10, and RV represents to sum of series resistance 22 of victim net 10. The model of FIG. 3 ignores the series resistance 28 and shunt capacitance 24 of aggressor network 12.
The model of FIG. 3 can be easily expanded as illustrated in FIG. 4 when net 10 is the victim of m aggressor nets. A model having the topology of FIG. 4 can be constructed for every victim net of any IC, with appropriate values for the lumped resistance and capacitance parameters CC1, CV and RV being derived from the RC extraction data for the victim and aggressor nets.
Huang teaches that, based on the model of FIG. 4, the peak crosstalk noise for any victim net of an IC can be estimated by evaluating a mathematical expression having the resistance and capacitance parameters of the model of FIG. 4 as independent variables. Since it is much quicker for a computer to evaluate the expression based on the model of FIG. 4 than to simulate circuit behavior of a model of the type illustrated in FIG. 2, Huang's approach significantly reduces the time needed to estimate crosstalk noise.
Huang also teaches to further reduce the time needed to estimate crosstalk noise in an IC by pre-screening the nets to eliminate nets are unlikely to have excessive crosstalk noise, and then calculating peak crosstalk noise only for the remaining nets. FIG. 5 illustrates a process flow suggested by Huang. Beginning at step 31, the nets are subjected to a screening process to select a first net of the IC as a victim net that could be subject to excessive crosstalk noise. During the screening process, the RC extraction data for each successive net is inspected to determine whether the net has a large loading capacitance or a short RC time constant. Huang teaches that signals conveyed by victim nets having large loading capacitances or short RC time constants are unlikely to be driven to false logic states by crosstalk noise and should be rejected as candidates for crosstalk noise calculations. When a suitable victim net is found (step 32), the RC extraction data is read into memory (step 33) and all of the other nets are then screened (step 34) to eliminate any nets that are unlikely to cause substantial crosstalk noise in that victim net. During the aggressor net screening process, the IC layout is analyzed to determine how distant each aggressor net is to the victim, and aggressor nets that are too distant from the victim are eliminated from consideration.
Having identified the aggressor nets that are sufficiently close to the selected victim net, the RC data for each identified aggressor net is read into memory (step 35). An RC extraction tool is then used to determine the coupling capacitances between each identified aggressor net and the victim net (step 36). The coupling capacitances, along with the RC data for the victim net, are then processed to calculate the peak crosstalk noise at the output of the victim net (step 37). The process repeatedly loops through steps 31-37 to calculate peak crosstalk noise for each net not eliminated by victim net screening step 31.
While Huang's approach reduces the time required to estimate crosstalk noise in the nets of an IC over methods employing circuit simulation, its crosstalk noise calculation is based on the simplified model of FIG. 4 that does not represent the behavior of the victim net output signal VO as accurately as the more complex model of FIG. 2.
Huang's process flow of FIG. 5 can be somewhat time-consuming because it may require a processor to repeatedly access a hard disk man times. A data file containing RC extraction database for a large, complicated IC is usually much too large to fit in the random access memory of a computer executing crosstalk calculation software. The computer must therefore store the RC extraction database file on a hard disk and read access that disk whenever it needs RC extraction data for any particular net. Since it takes a substantial amount of time for the computer to read access a disk drive, disk access time can be quite significant in comparison to the time the computer needs to compute peak crosstalk noise for the net. An inspection of the prior art process flow of FIG. 5 reveals that it may be necessary for computer carrying out the crosstalk analysis procedure to read access the RC data for any given net many times. The RC extraction data for a given net of the IC is read once during step 31 because the capacitance and resistance of the net are factors used in screening the nets to determine which nets are likely to be substantially influenced by crosstalk. The RC data for that net is then read again at step 33 when the net is identified as a victim for which crosstalk noise must be calculated because the RC characteristics of the net are used in the crosstalk calculation. The RC data for a net is read yet again at step 35 whenever that net is identified as an aggressor with respect to any victim net. Thus, for example, when a net is proximate to fifteen other nets, a computer carrying out the crosstalk calculation process could read access that net's RC data seventeen times, once during victim net screening step 31, once during step 33 after having been identified as a victim net, and once at step 35 for each of the other nets that are identified as its victim.
What is needed is a method for estimating crosstalk noise that is nearly as accurate those based on simulation of the model of FIG. 2, but which requires less computation time and relatively fewer disk accesses.